In a conventional chip packaging process, a chip is placed on a carrier substrate such that the solder balls of the chip are in direct physical contact one-to-one with substrate pads of the carrier substrate. Then, the temperature of the carrier substrate and the chip is raised to a bonding temperature where the solder balls of the chip melt and bond to the substrate pads. After that, the carrier substrate and the chip are cooled down. Because the CTE (coefficient of thermal expansion) of the chip is smaller than the CTE of the carrier substrate, the difference between shrink rates of the carrier substrate and the chip during the cooling down results in stress on the solder balls and underlying structures of the chip. Therefore, there is a need for a structure (and a method for forming the same) in which the chip packaging process is performed with reduced stress on the solder balls and underlying structure of the chip.